1. Field of the Invention
Apparatuses and methods consistent with the present invention relates to a phase-locked loop (PLL), and more particularly, to a phase-locked loop for stably adjusting a frequency band of a voltage-controlled oscillator and a phase locking method.
2. Description of Related Art
FIG. 1 is a block diagram illustrating the inner construction of a related art phase-locked loop (PLL) 100.
Referring to FIG. 1, the PLL 100 includes a phase/frequency detector (PFD) 110, a charge pump (CP) 120, a low-pass filter (LPF) 130, a voltage-controlled oscillator (VCO) 140, a frequency divider 150, and a frequency band selector 160.
The PLL 100 receives an input clock signal CLK1 and outputs an output clock signal CLK2 having a frequency higher or lower than that of the input clock signal CLK1. The PFD 110 compares the input clock signal CLK1 with an output signal which is fed back to the PFD 110 from the VCO 140 via the frequency divider 150, and generates a comparison result output signal in accordance with the phase and frequency difference between the input clock signal CLK1, and the output signal fed back via the frequency divider 150. Then, the compared output signal is processed in the CP 120 and the LPF 130, which subsequently provides a control voltage VCTRL to the VCO 140. At this time, the VCO 140 is phase-locked at a certain frequency by the control voltage VCTRL. By such a feedback operation, a frequency band of the output clock signal CLK2, which is phase-locked in the VCO 140, is adjusted to have a certain target frequency (FVCO) in accordance with the operation of a frequency band selector 160. Such a disclosure is described in detail in Japanese Patent Laid-Open Publication No. 2001-251186.
FIG. 2 is a graph illustrating the operating frequency band of the VCO 140 of FIG. 1.
Referring to FIG. 2, the frequency band of the output clock signal CLK2 from the VCO 140 is determined by output digital values 000 to 111 of the frequency band selector 160 in accordance with the control voltage VCTRL. When the control voltage VCTRL output from the LPF 130 reaches a target voltage VT, the frequency of the output clock signal CLK2 is phase-clocked at the target frequency FVCO within a corresponding frequency band.
For example, as shown in FIG. 3, when the control voltage VCTRL fluctuates between VL and VH over time, the VCO 140 alters the frequency band of the output clock signal CLK2 thereof depending on the output digital values of the frequency band selector 160 several times. The frequency band selector 160 allows the frequency band of the output clock signal CLK2 to alter to a high frequency band or a low frequency band at a time point where the control voltage VCTRL is larger than VH or is smaller than VL. Generally, like the waveform 310, after the frequency band of the output clock signal CLK2 of the VCO 140 has gone through a period of ringing/fluctuation, the control voltage VCTRL reaches the target voltage VT and the frequency of the output clock signal CLK2 is phase-locked at the target frequency FVCO.
In the PLL 100, a ringing/fluctuation may exist in the control voltage VCTRL, as shown in FIG. 3, depending on a manufacturing condition or an operation temperature when a circuit is fabricated in slightly different environments. However, such a related PLL has a shortcoming in that like the waveform 320, if the frequency band is changed each time the ringing/fluctuation peak exceeds a threshold VL/VH, the control voltage VCTRL does not reach the target voltage VT and the frequency of the output clock signal CLK2 is not phase-locked at the certain target frequency FVCO.
In addition, for the PLL 100 there occurs a problem in that if a response time of basic PLL circuits 110 to 150 as shown in FIG. 1 is not taken into consideration, the frequency of the output clock signal CLK2 is not phase-locked at the certain target frequency FVCO since the response time of basic PLL circuits 110 to 150 is longer than a response time of the frequency band selector 160. For example, the time spent for the frequency band selector 160 to change the output thereof for the purpose of changing the frequency band of the output clock signal CLK2 is short at an interval where the ringing/fluctuation peak goes beyond the threshold VL/VH, but the time spent for the control voltage VCTRL to be output from the LPF 130 by reflecting this is as long as the time spent for the feedback operation of the basic PLL circuit 110 to 150. Therefore, the output of the frequency band selector 160 for the purpose of changing the frequency band of the output clock signal CLK2 is changed again prior to its reflection of the control voltage VCTRL at an interval where the ringing/fluctuation peak goes beyond the threshold VL/VH, thereby making the phase-locking of the frequency of the output clock signal CLK2 unstable.